The present invention relates to testing multiple data packet signal transceiver devices under test (DUTs), and in particular, to testing multiple DUTs with a shared tester to maximize tester use and thereby minimize test time.
Many of today's electronic devices use wireless technologies for both connectivity and communications purposes. Because wireless devices transmit and receive electromagnetic energy, and because two or more wireless devices have the potential of interfering with the operations of one another by virtue of their signal frequencies and power spectral densities, these devices and their wireless technologies must adhere to various wireless technology standard specifications.
When designing such wireless devices, engineers take extra care to ensure that such devices will meet or exceed each of their included wireless technology prescribed standard-based specifications. Furthermore, when these devices are later being manufactured in quantity, they are tested to ensure that manufacturing defects will not cause improper operation, including their adherence to the included wireless technology standard-based specifications.
During testing of data packet signals sent by a DUT to a tester, the packets initially transmitted, e.g., when an otherwise properly operating DUT′ transmitter first begins transmitting, its power will vary, increasing and decreasing until it “settles” to the intended nominal power, with any further power variations normally deemed to be insignificant. At that time, after settling, the tester then begins capturing data packets for analysis. Earlier data packets captured during the settling time are essentially ignored for purposes of the analysis. However, their capturing nonetheless ties up capture and analysis resources of the tester. Thus, from a tester utilization perspective, the analysis functions of the tester remain idle during the transmitter power settling interval, and thus detracts from overall tester utilization.
Current attempts to optimize tester use during testing will often predefine a test step sequence that a DUT will execute during a test, usually based on either signal transmission time or number of transmitted data packets. Consequently, the DUT will only execute a given test sequence for a predetermined time interval. When trying to test multiple DUTs contemporaneously, e.g., in parallel, one needs to design the test sequence to allow DUT performance to be analyzed in a worst case scenario where all DUTs request access to hardware at the same point in time. However, in most cases such a worst-case scenario will not occur, though all DUTs continue to execute their test sequences to satisfy the worst-case scenario. Hence, proportionally, a significant amount of test time is unproductive as the tester captures data packets unsuitable for analysis.